1. Field of the Invention
The present invention relates to an information processing device for processing information which is made up of a plurality of processors each having a register file formed on a single semiconductor chip.
2. Description of the Prior Art
Conventionally, in an information processing device of FIG. 1 including a plurality of processors 10 (or a multi-processor information processing device) formed on a single semiconductor chip, a cache memory 11 is incorporated for each processor 10 and each cache memory 11 is electrically connected to a main memory 13 through a common bus 12. In the prior art, there is a problem that the conventional information processing device has a poor execution efficiency or poor performance because data is transferred between the processors 10 through the main memory 13, so that latency of a memory access operation becomes low.
In order to avoid this drawback described above and so that the processors 10 perform efficiently, data transfer operation must be performed between the cache memories 11, not through the main memory 13, as much as possible. In other words, the number of accesses to the main memory 13 must be reduced in the conventional information processing device. But, this causes some limitations on programs to be executed in the conventional information processing device.
Furthermore, the cache coherency problem between the cache memories 11 and the main memory 13 becomes so complicated that it must be required to form a complicated configuration of the conventional information processing device.
As described above, in the conventional information processing device having a plurality of processors, there is the drawback that the instruction execution efficiency becomes low because the data transfer operation between the processors 10 is performed through the main memory whose operation speed is low and a large amount of data transfer time between the processors 10 is required.
Moreover, because each processor has the cache memory and it must be required to store the same data into the main memory and the cache memories in the conventional information processing device as shown in FIG. 1, designers must design complicated hardware configurations.